The field of the invention is computers for circulating Fast Fourier Transforms (FFTs), and in particular those for which power dissipation must be unusually low and both resolution and reliability unusually high. The FFT is one of the most commonly used algorithms for spectral analysis, emitter identification, digital filtering and signal reconstruction. Apparatus for performing the FFT process includes memories, delay registers, arithmetic elements, "dual path switches" used as interfaces between arithmetic elements, etc.
"Dual path switches" (DPSs) are an important part of the present invention. They are multiplexers or sets of selector switches that steer digitized signals to one channel or another, with appropriate cycle delays. DPSs are used in many electronic warfare, communications, and electronics intelligence systems.
Many DPS interfaces are used in an FFT processor, as can be shown by a 1024-sample FFT circuit, which is sometimes referred to in this field as a "benchmark". The benchmark's processor may be composed of 10 processing stages (1024=2.sup.10). Where a 32-bit data format is employed, each stage requires two words of 32-bit data apiece, i.e., 32 bits for in-phase data and 32 bits for quadrature-phase data. Four 8-bit DPSs are required to implement each 32 bit word, hence 8 DPSs are required per stage. As a result, 80 DPSs are required for a 10-stage FFT benchmark of that type.
The receiving apparatus for a multiple channel phased antenna array, for example a 16 channel system, may have more than 1,280 DPSs. The improvement in size, power, processing throughput, and reliability of such a large system can be very great when a smaller, faster, and more reliable DPS gate array of lower power consumption is employed.